The present invention relates generally to multiple processor computer systems. More particularly, the invention is directed to systems and methods for booting/starting/restarting/resetting a multiple processor system characterized by the presence of a shared global memory and a multiplicity of relatively independently operable processors having individualized resetting and booting resources.
Systems composed of multiple but coordinated processors were first developed and used in the context of mainframes. More recently, interest in multiple processor systems has escalated as a consequence of the low cost and high performance of microprocessors, with the objective of replicating mainframe performance through the parallel use of multiple microprocessors.
A variety of architectures have been defined for multi-processor systems. Most designs rely upon highly integrated architectures by virtue of the need for cache coherence. In such systems cache coherence is maintained through complex logic circuit interconnection of the cache memories associated with the individual microprocessors to ensure data consistency as reflected in the various caches and main memory.
A somewhat different approach to architecting a multi-processor system relies upon a relatively loose hardware level coupling of the individual processors, with the singular exception of circuit logic controlling access to the shared global memory, and the use of software to manage cache coherency. An architecture which relies upon software managed cache coherency allows the designer to utilize existing processor hardware to the maximum extent, including the utilization of the processor hardware integrated booting/starting/restarting/resetting resources. This independence of the processors also lends itself to multi-processor systems with accentuated levels of availability, in that such independence facilitates continuity of system operation in the presence of failures or removals of one or more processors. Coordination in the access to, and coherency with, a shared global memory is of course somewhat more difficult with such independence of processors.
A fundamental problem which arises with such individualized processor multi-processor systems involves the coordination to accomplish system wide booting. Not only are the multiple processors designed and configured to accomplish individualized starting, but such starting must also incorporate the effects of an asynchronous common start signal. The asynchronous signal is usually derived from the status of the power supply. The multi-processor system must also have resources to synchronize the processors undergoing individualized starting to a master clock, and devices and methods to insure initialization and testing of all the processor as well as the shared global memory. Accomplishing this in the face of a failure in one or more of the processors complicates the management of the booting operation, in that booting responsibilities cannot be permanently allocated to selected ones of the processors.